1. Field of the Invention
Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. More particularly, example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a complementary metal-oxide semiconductor (CMOS) transistor.
2. Description of Related Art
As demand for semiconductor devices having high operational speeds and large capacitances increases, semiconductor manufacturing processes have been developed to improve a degree of integration, reliability and/or response speeds of the semiconductor devices. To increase the integration degree of a transistor, a gate insulation layer having a thin equivalent oxide thickness (EOT) has been employed in manufacturing the transistor. When a silicon oxide layer used for forming the gate insulation layer has a physically thin thickness, leakage current between a gate electrode and a channel may increase and a defect in the semiconductor device may result.
A gate electrode formed using a metal increases the response speed. When the gate electrode is formed using polysilicon in a conventional method, threshold voltages (Vth) of an n-type metal-oxide semiconductor (NMOS) transistor and a p-type metal-oxide semiconductor (PMOS) transistor can be adjusted by changing the type and amount of dopants, where the work function of polysilicon varies in accordance with the type and amount of impurities doped into polysilicon. The gate electrode formed using polysilicon may cause a gate depletion problem.
When the gate electrodes of the complementary metal-oxide semiconductor (CMOS) transistor are formed using a metal, the gate depletion problem may be overcome, but threshold voltages of the NMOS transistor and the PMOS transistor cannot be readily adjusted using dopants. For example, the NMOS transistor and the PMOS transistor may be formed by manufacturing the gate electrodes of the NMOS transistor and the PMOS transistor to different thicknesses and/or using different types of metal, respectively. While the gate electrodes of the NMOS transistor and the PMOS transistor, which have different materials and thicknesses, are formed on a substrate, a gate insulation layer or an active region of the substrate adjacent to the gate electrodes may be damaged, for example, by a dry etching process.
A method of forming a CMOS transistor is disclosed in U.S. Patent Application Publication No. 2004/0245578. According to the publication, a buffer layer is formed on a gate dielectric layer, and then a metal layer used for forming a gate electrode of an NMOS transistor is formed on the buffer layer. An additional metal layer is formed on a substrate in a NMOS region and a PMOS region, and the metal layers are patterned by performing an etching process to form gate electrodes in the NMOS region and the PMOS region. The above-mentioned publication merely discloses that damage to the gate dielectric layer is reduced by using the buffer layer formed on the gate dielectric layer.
Therefore, a need exists for a method of manufacturing a semiconductor device having a complementary metal-oxide semiconductor (CMOS) transistor without damaging a substrate and/or a gate insulation layer.